The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating or dielectric materials to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step. The most frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulating materials to avoid capacitance coupling between the metal interconnects.
Current technology involves forming vias and trenches that have sub-micron dimensions which can be 0.25 microns or less in width. One of the more promising low k dielectric materials is organosilicate glass (OSG) which is a silicon oxide that is doped with carbon and hydrogen atoms. While SiO2 which has been traditionally used as a dielectric material in older technologies has a dielectric constant of about 4, OSG has a k value between 2 and 3 and thereby provides a much needed reduction in capacitance coupling between wiring. OSG is available as Black Diamond™ from Applied Materials, CORAL™ from Novellus, or can be obtained by different trade names from other manufacturers.
One of the problems associated with OSG is that the material is susceptible to damage during commonly used etching and cleaning steps. For instance, a photoresist layer is typically patterned above the OSG dielectric layer in a damascene process. A via hole or trench opening in the photoresist pattern is then etch transferred into the OSG layer. Typically, the photoresist is stripped with an oxygen containing plasma in a subsequent step. However, the oxygen plasma is capable of etching the sidewalls of the pattern in the OSG layer as it reacts with carbon and hydrogen atoms. This reaction can readily increase the critical dimension (CD) of the opening and transform a vertical sidewall into an undesirable sloped sidewall. This issue is addressed in U.S. Pat. No. 6,426,304 where a H2/N2 plasma is employed to strip a photoresist above an OSG layer. According to an FTIR analysis, there is less than a 2.5% change in OSG composition after the plasma treatment.
In U.S. Pat. No. 6,168,726, an oxidized organosilane dielectric layer is etched with a fluorocarbon and inert gas based plasma on a pedestal electrode that is RF biased. Optionally, a carbon volatilizing gas such as O2 or N2 is added in a second step.
A method of protecting an OSG layer is described in U.S. Pat. No. 6,410,426 in which a Ti(1-X)AlXN capping layer is deposited on an OSG dielectric layer in a damascene scheme and functions as a hard mask during an etch sequence that includes an OSG etch with C4F8, N2, and CO plasma.
Yet another method of preventing degradation in a low k dielectric layer such as OSG is found in U.S. Pat. No. 6,331,479. Two etch stop layers are formed between a first and second dielectric layer and two cap layers are deposited on the second dielectric layer while forming a metal interconnect. This scheme is likely to be costly because of additional layers and extra process steps.
Another concern with using OSG in a damascene structure is that the etch rate of OSG is close to that of a silicon carbide capping layer that is often used between the conductive layer and dielectric layer in a damascene stack. A representative process flow is depicted in FIGS. 1a-1e that demonstrates a serious issue with an OSG dielectric layer. Referring to FIG. 1a, a substrate 1 is provided that contains a conductive layer 2 and active and passive devices (not shown). A silicon carbide layer 3 is deposited by a chemical vapor deposition (CVD) technique and serves to protect conductive layer 2 during subsequent processing steps. An OSG layer 4 is deposited by a CVD or plasma enhanced CVD method on silicon carbide layer 3. A bottom anti-reflective coating (BARC) 6 is typically spin-coated or CVD deposited on OSG layer 4 in order to improve the process window in a subsequent photoresist patterning step. Next, a photoresist layer 7 is coated and patterned to form a via opening 8.
Referring to FIG. 1b, the via opening 8 is etched through BARC layer 6 and OSG dielectric layer 4 and stops on silicon carbide layer 3. Photoresist layer 7 and BARC 6 are stripped and then a wet clean step is used to remove any residues within via hole 8.
In FIG. 1c, a BARC 9 is spin coated on dielectric layer 4 and some partially fills via hole 8. The BARC 9 is usually hardened by baking to about 225° C. so that it becomes inert towards a photoresist layer 10 which is then coated and patterned to form a trench opening 11 above via hole 8.
Referring to FIG. 1d, the trench pattern 11 is etched into OSG layer 4 to a predetermined distance that is less than the depth of via hole 8. Photoresist layer 10 and BARC 9 are removed and a wet clean step is used to remove any residues from via hole 8 and trench opening 11.
In FIG. 1e, the exposed portion of silicon carbide layer 3 in via hole 8 is removed by a plasma etch that typically contains a fluorocarbon gas. However, the plasma also attacks the OSG layer 4 along the sidewalls of via hole 8 and trench 11 because of the carbon and hydrogen content in OSG layer 4. This reaction causes the top corners of trench 11 and via hole 8 to become rounded and the sidewalls become sloped as OSG layer 4 is etched away. Moreover, the horizontal surface of trench 11 is pitted. As a result, the CD of the via hole 8 and trench 11 are increased because of the loss of OSG layer 4 and this causes a loss of reliability in the final device. Therefore, an improved method of forming a dual damascene structure containing an OSG dielectric layer is needed to achieve the desired interconnect performance in new technologies.
Other efforts to improve the processing capabilities with an OSG dielectric layer are described in U.S. Pat. No. 6,410,437. A via hole is etched through an OSG layer and stops on a silicon carbide layer. First a low selectivity etchant removes a majority of the exposed OSG layer to transfer the hole opening and then a high selectivity etchant which is a plasma derived from a mixture of Ar, N2, and C4F8 completes the via etch. U.S. Pat. No. 6,107,192 describes a reactive preclean process prior to metallization for sub-0.25 micron applications. A soft plasma etch including fluorine and oxygen radicals cleans SiO2 based dielectric layers. A second step involving hydrogen radicals reacts with metal oxide residues to produce a clean metal surface and water as a by-product.